1. Field of the Invention
The present invention is a method and apparatus for determining the position of devices in a circuit layout. More specifically, the present invention is a method and apparatus for establishing constraints for devices of a circuit that can be utilized to automatically determine the exact relative position of the devices.
2. Description of Related Art
In designing analog circuits to be manufactured using semiconductor processes, a number of techniques are used. Analog semiconductor circuits are often designed to use the ratios between devices (which can be carefully controlled) rather than the absolute values of those devices. Often, for devices in a semiconductor design, the absolute value accuracy can only be kept to 10%-40%. However, the ratio between devices can be controlled to near 0.5% accuracy if correct techniques are used. One of the most commonly used techniques is known as “Matching”. Matching can be implemented by a variety of techniques in the physical design of analog semiconductor circuits. All of the techniques for implementing matching involve having two or more devices share some common property. To this end, there are a large number of possible physical implementations for a single device in a circuit which are all roughly electrically equivalent. For example, transistors T1 and T2 shown in FIG. 1 are roughly electrically equivalent because their primary characteristics, (width) W and (length) L, are the same. These two characteristics, W and L (or the Width of the Source and Drain and the Length of the Gate of the transistor) are the primary electrical characteristics that are used to design devices. Two transistors which have the same W and L will exhibit roughly the same electrical behavior.
With reference to FIG. 2, and with continuing reference to FIG. 1, in certain circuit designs, however, such as analog circuit designs, the electrical behavior sometimes needs to be much closer than roughly equivalent. For example, in FIG. 1, transistor T1 will have different total areas for Source and Drain than transistor T2. This will affect the capacitance to the substrate for the contacts of transistors T1 and T2. In turn, these differing capacitances will affect the electrical behavior of transistors T1 and T2 so they are not exactly the same. In other words, specifying the same W and L for two devices may make their rough electrical behavior equivalent, but it does not make their detailed electrical behavior the same. This leads to a first type of Matching, referred to as “Device Matching”, where a set of devices is all implemented with the exact same geometry. For example, if Device Matching is desired, two devices, e.g., transistors T1 and T3 in FIG. 2, having the same W and L parameters would both be implemented using the same geometry. In contrast, devices, e.g., transistors T1 and T2 in FIG. 1, having different device geometries are not device matched.
With reference to FIG. 3, and with continuing reference to FIG. 1, the detailed electrical behavior of devices on semiconductor surfaces can also change due to manufacturing processes. In order to keep the behavior of these devices as close to electrically equivalent as possible, other types of matching are required. For example, a common semiconductor process variation can cause the top edge of a layer to move relative to the rest of the edges. Thus, for example, if the top edge of all shapes on the polysilicon layer shift downward by a small amount, then there is a different electrical effect on the transistors T1 and T2 shown in FIG. 1. Specifically, transistor T1 will have its L reduced by some small amount. However, in transistor T2, the top edge of the polysilicon layer is simply the connection between two sections of the gate. Therefore, that connection will get slightly narrower, which will increase its resistance but will not affect the W or L of transistor T2. The change in L of transistor T1 and the absence in the change in L of transistor T2 will create an electrical mismatch between the detailed electrical behavior of transistors T1 and T2. This effect can be overcome by ensuring each transistor has the same orientation whereupon these types of process variations affect each device the same way. This is known as “Orientation Matching”. In order to make these transistors T1 and T2 match orientation, transistor T1 in FIG. 1 would need to be rotated 90 degrees to the orientation shown in FIG. 3.
With reference to FIG. 4, and with continuing reference to FIG. 1, other types of process variations change over the area of the circuit. Therefore, two devices which are close to each other will show less variation than two devices that are far apart. The amount of doping that occurs in the substrate is a good example of a process-dependent quantity that can vary over distance. This doping amount will affect the ease with which current flows through the device. Obviously, this will impact the equivalence of the two devices' electrical behavior. Therefore, if two devices must be very well matched, they should be placed close to each other. This is known as “Proximity Matching”. In order to make transistors T1 and T2 match proximity, they would be placed next to each other as close as possible, as shown in FIG. 4. They would also usually be aligned in either the X or Y direction.
With reference to FIG. 5, and with continuing reference to FIG. 1, one special case of matching, which is used when only two devices need to match, is known as “Symmetry Matching”. Two devices, e.g., transistors T2 and T4 in FIG. 5, that should be symmetric are typically device matched. They also typically use a special case of orientation matching where the orientation is mirrored. Additionally, the two devices will usually be aligned in one dimension an equal distance from a specified symmetry line, as shown in FIG. 5.
FIG. 6 shows a combination of Device and Orientation Matching. FIG. 7 shows a combination of Device, Orientation and Proximity Matching.
The foregoing matching types are utilized in an attempt to achieve higher levels of electrical equivalence between pairs and sets of devices in circuits. Groups of devices using all three matching types or pairs of devices having symmetry have the highest level of electrical equivalence. All of these matching techniques will reduce the percent variation between the ratio of devices in the circuit.
Currently, most circuit designers implement their semiconductor layout manually. Therefore, these matching techniques are performed by hand. However, it is sometimes difficult to verify that the matching techniques have been correctly performed. This is especially true with detailed geometric constraints such as symmetry or proximity matching.
Another common technique to assure that a physically implemented circuit behaves as expected is to specify the relative position of devices to each other. This technique places devices in the same relative positions as they are on the schematic. This ensures that the interconnections between these devices will be short and that the devices will be placed close to each other. Circuit designers also often place devices as they appear on the schematic purely for simplicity. In addition, designers often align devices to allow for better layout aesthetics and easier routability of interconnections. FIGS. 8(a) and 8(b) show a schematic fragment and a layout, respectively, with devices T1 to T5 in the same relative positions.
It should be noted in FIGS. 8(a) and 8(b) that many of the matching concerns described above also apply. For example, devices T1 and T3 may be specified to be symmetrical. Devices T1 and T4 may be matched in terms of proximity, device and orientation. Similarly, devices T3 and T5 may be matched in terms of proximity, device and orientation. This set of complex matching is possible in current designs implemented by designers since the devices and circuits are designed completely manually. This allows complete freedom to implement any of these concepts of topological placement along with different types of matching.
Some current automatic layout methodologies allow for constraints that specify relative topological placement. These constraints take the form of, for example, Device T1 ‘isAbove’ Device T2, or Device T1 ‘isLeft’ of Device T2, etc. These methodologies also allow for some level of alignment constraints (which give a portion of the matching techniques). However, these layout methodologies are not complete systems that allow for topological layout placement with integrated support for different matching techniques. In addition, the specification of a large set of topological constraints could easily become impossible to satisfy, as well as quite complex and awkward to implement.
Analog circuit design for semiconductor circuits requires a high degree of matching along with the ability to specify relative locations for placement. These two capabilities are necessary to consistently create working layouts from schematic descriptions of circuits. The most prevalent method for creating layouts for analog circuits is a completely manual process. This process has the greatest flexibility to implement all of the techniques described above. However, it is also the most time consuming. As the layout of analog circuits moves toward more automation, these techniques also require automation. The few techniques that are currently implemented in automatic layout systems do not address all the requirements described above.
For example, a schematic representation of a design simply has symbols for each device, but actual geometric information does not yet exist. Therefore, in order to specify the placement of devices relative to each other, specifications must be utilized that are relative to each device. To this end, it cannot simply be stated that device T1 is placed at position x=100, y=100, and that device T2 is placed at position x=100, y=200 since this placement may be Design Rule incorrect according to technology rules for the targeted process, or the devices may even end up overlapping (depending on the height of device T1 in this example). Therefore, it is desirable that placement rules be expressed in a technologically independent way. Typically, this has taken the form of sets of pairwise constraints, e.g., device T2 ‘isAbove’ device T1. This means that device T2 is a specific distance above device T1, aligned on their centers. Typically, this specific distance is determined by the technology rules. For example, the devices might be placed at a minimum design rule correct (DRC) distance. However, once the problem is more complicated than a single pair of devices, it becomes easier to specify a set of impossible constraints. A simple example of a set of impossible constraints is the following set of constraints:                Device T2 isAbove Device T1;        Device T3 isAbove Device T2; and        Device T1 isAbove Device T3.        
In this example, it is fairly easy to detect that device T1 cannot be below device T2 AND device T3. However, it is indicative of the larger problem. Once other constraints, such as symmetry, are included, the problem becomes even more difficult. For example:                Device T1 isSymmetric with Device T2;        Device T3 isSymmetric with Device T4;        Device T3 isAbove Device T1; and        Device T2 isAbove Device T4.        Assume only a single vertical symmetry line, and the constraint “isAbove” also implies vertical alignment.        
As shown in FIG. 9, device T3 cannot be symmetric with device T4 AND above device T1 when device T2 is above device T4.
It is, therefore, desirable to overcome these problems and others by providing a method and apparatus for specifying relative topological constraints for devices of a circuit that avoid illegal sets of constraints and enable the relative topological geometry of the devices to be determined automatically. Still other desirable features of the present invention will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.